Principal Engineer, CMOS Design

Practical experience architecting / designing high speed CMOS baseband transceivers (e.g. OC-192, XAUI, Backplane, Cable). Required knowledge and experience designing clock multiplier PLL’s, data and clock recovery circuits, low noise oscillator design, serializers / de-serializers, high-speed low-resolution data converters, CML IO and clock distribution networks, and other high speed communication blocks.

A thorough understanding of high speed chip assembly issues relating to substrate noise, de-coupling strategies, power routing, package parasitic, and design for test is fundamental. A strong background in signal processing for communication systems is highly desirable.The candidate must know and be experienced with industry standard CAD tools for circuit simulation schematic capture, etc. Experience with Matlab and/or Simulink , Verilog coding, etc. is highly desirable. The successful candidate will lead a team designing very high speed mixed-signal CMOS integrated circuits for high bit rate systems that are targeted at backplane, optical interconnect, or similar applications. The job entails helping to define the product, performing system level behavioral simulations, extensive transistor level design and simulation, evaluation and help with introduction to manufacture. The candidate will work closely with customers and marketing. Previous experience in high-speed analog and digital circuit design. MSEE or PhDEE.

Location: Portland OR

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