CMOS Design Engineer

High-speed analog CMOS design with demonstrated ability to lead and develop architectural / circuit solutions for complex transceiver communication blocks such as CMOS PLLs, phase interpolation data recovery systems, auto-zero’d high speed receivers, quadrature LC-VCOs with digital calibration, CML clock distribution networks, clock multiplier units (e.g. phase /frequency detectors, charge-pumps, active loop filters, low jitter clock divider units, etc.), and high speed CML-type wired line drivers.

Good grasp of communication and digital signal processing fundamentals with a solid background in mathematics and the ability to approach design problems analytically. 

BSEE, MSEE or PhDEE

Location: Portland OR

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